Design and Implementation of Soft Error Resilient 14T SRAM Cell
نویسندگان
چکیده
منابع مشابه
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read ope...
متن کاملDesign and Implementation of a Soft-error Resilient OSEK Real-time Operating System
Advances in manufacturing processes steadily reduce the structure size of computer chips, which improves their processing power. However, this smaller size also increases the likelihood of soft-errors, such as the flip of a single bit in memory. If such an error remains undetected, it can result in invalid system behavior. This is unacceptable for dependable systems which have strict reliabilit...
متن کاملA BICS Design to Detect Soft Error in CMOS SRAM
This paper presents a Built In Current Sensor (BICS) design to detect soft error under both standby and operating condition in Complementary Metal Oxide Semiconductor (CMOS) Static Random Access Memory (SRAM). BICS connected in each column of SRAM cell array detects various values of current signal generated by particle strike. The generated current value is then compared with the reference val...
متن کاملSoft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell
This paper describes a soft-error tolerant and marginenhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, str...
متن کاملImplementation of High Reliable 6T SRAM Cell Design
Memory can be formed with the integration of large number of basic storing element called cells. SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit. Modified read and write circuits were proposed in this paper to address incorrect read and write operations in conventional 6T SRAM cell design available in open literature. Design of...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Evergreen
سال: 2023
ISSN: ['2189-0420', '2432-5953']
DOI: https://doi.org/10.5109/6793669